Complementary metal oxide semiconductor (CMOS) Input/output buffers which perform the interface between a packaged digital device chip and other such device chips must be able to withstand all anticipated conditions which might occur in normal usage as well as some conditions which could occur only under certain system power supply failure modes. One of the latter conditions, well known to designers, is the condition under which the system supply voltage fails and causes voltage stress, originating from an external load, to be impressed on the input, output, or input/output (I/O) buffer circuitry. This application problem has been made even more difficult in sub-micron CMOS circuitry operating on low voltage power supplies (3.3 volts, for example) but having the requirement that it must drive external circuitry biased with higher voltage supplies (5.0 volts or higher). A number of circuit configurations have been developed to address this problem.
One technique widely used to allow low voltage rating transistors to interface to higher voltage is to replace single transistors, which would otherwise have to withstand full voltage stress, with stacked or cascoded multiple transistors across which the stress may be distributed. The major difficulties of prior art solutions have been the effective sensing of the failed-supply condition and the proper biasing of the cascode protection transistors to allow both the required protection in the failed-supply state, and also the correct buffer operation in the normal state. Some chip suppliers have supplied buffers which have been designed using these and other supplementary circuit techniques, yet the buffers are normally not sufficiently robust that the supplier can claim fail-safe operation. Fail-safe operation means unconditional circuit reliability after extended supply voltage failure with high voltage signal levels applied to input/output pins.
Sub-micron chips having buffers without fail-safe protection will usually suffer catastrophic failure when the normal chip supply voltage fails for an extended period, if any input, output, or input/output buffer has a positive applied external voltage in the 5.0 volt range. This failure is usually the result of a gate oxide voltage breakdown but can also result from a drain-source impressed voltage beyond normal rated limits.
Providing fully fail-safe operation for CMOS input/output buffers is an extension to or generalization of the solution a more basic problem, namely, that of providing high voltage tolerant operation in low-voltage (3.3 volt supply) CMOS. Briefly stated, 5 volt tolerant operation means that a circuit, designed for a 3.3 volt power supply, is able to drive a load or be driven from a source consisting of a resistor connected to a 5 volt power supply. Specifications for 5 volt tolerant circuits define maximum output leakage current flow in the `high` or `off` state, or maximum input leakage in the input `high` state. No appreciable input circuit or output circuit degradation is permitted. Note that a 5 volt tolerant circuit specification does not guarantee protection from the more stringent fail-safe condition, namely that the circuit must not sustain degradation when the normal V.sub.DD supply for the circuit fails, but applied voltage up to 5 volts or higher, at the bond pad from other chips external to the chip in question persists.
Circuits which are operated from a 3.3 volt supply often have this requirement so that they can be used in systems along with circuits which are operated from a 5 volt supply. Essentially, protection for the input circuit or output circuit is derived from the placement of a series transistor protection device between the circuit being protected and the bond pad. The biasing of the gate terminals of these series protection transistors has, in prior art, been ineffective to adequately protect all transistors at the input, output or input/output interface from voltage stress exceeding V.sub.OX.sub..sub.-- .sub.MAX (the maximum gate oxide voltage) in all failure modes conditions. Also, bias circuits operating in the highly irregular V.sub.DD failed state must be free from other conditions such as latch-up resulting from semiconductor-controlled-rectifier (SCR) action of parasitic transistors present in the device structures. These effects have also limited the application of prior art solutions.